Tik-76.115 Individual Project: Guinea Pig
$Id: overview.html,v 2.5 1996/04/22 14:16:34 hynde Exp $

Test Logic - Overview

Test Logic is the heart of the Guinea Pig system when a test is in progress. It communicates with Sound Player, Testee UI and Tester UI using sockets. It also communicates with the Test Creation module by reading in a test configuration file when it starts. It is also responsible for starting the other processes of the Guinea Pig system.

1 · Architecture

Test Logic is be implemented in Python using an object oriented approach to hide as much of the raw communication events behind objects as possible. After the initialization phase Test Logic is an event driven system driven by the packets it receives through its communication channels. It also contains the code to do decisions that are needed when the test is in progress. For example, in the audiometry test it will be responsible for the selection of the playing parameters for the sample to be played next based on the testee responses.

(More information: Test Logic: Architecture)

2 · Communication with other subsystems

Communication with other parts of the system (Sound Player, Testee UI) is done using python modules that have been written for that purpose (See: Sound player's and Testee UI's python interfaces.) These modules hide the underlying communication protocols and provide an easy object oriented interface.

3 · Real time requirements

Test Logic will be programmed so that it won't have to run on the same physical machine as Testee UI and Sound Player are running. Test Logic will have response time requirements in the 100 ms range. For most of the tests this will be perfectly adequate. Testee UI and Sound Player should be running on the same machine to enable us to record timestamps of Testee UI and Sound Player using the same physical reference clock. This clock could also be used to better syncronize the processes if some test would need such a synchronization. Linux on a Pentium processor provides system clock accuracy in the 1ms range by using the clock cycle register inside the processor.

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